Buffer management for data transfers between a host device and a storage medium

ABSTRACT

Systems and methods for transferring data between a host device and a storage medium are provided. In one implementation, a system for transferring data between a host device and a storage medium includes a host interface that receives from the host device a command to transfer data between the host device and the storage medium, a buffer that temporarily stores data that is transferred between the host device and the storage medium, a first register that stores a value for tracking a number of data units that have been transferred into the buffer but that have not yet been transferred out of the buffer, a second register that stores a value for incrementing a value contained in the first register, and a third register that stores a value for decrementing a value contained in the first register.

FIELD OF THE INVENTION

The present invention relates to data transfers between a host deviceand a storage medium.

BACKGROUND OF THE INVENTION

Memory controllers are used for transferring data between a host deviceand a non-volatile semiconductor memory device. Such memory controllerstypically contain a buffer for temporarily storing data that is in theprocess of being written to or read from the memory device. Errorssometimes occur during data transfers between the host and the memorydevice. Some errors may occur when data that is in the buffer isoverwritten prior to being transferred out of the buffer. Other errorsoccur when an attempt is made to transfer the wrong data or non-existentdata out of the buffer. Therefore, there exists a need for systems andmethods for buffer management that solve these and other problemsassociated with memory controllers.

SUMMARY OF THE INVENTION

The present invention relates to systems and methods for transferringdata between a host device and a storage medium. In this regard, anembodiment of one such method includes receiving from a host device acommand to transfer data between the host device and a storage medium,and storing in a register a value for determining a buffer's fullness.

An embodiment of a system for transferring data between a host deviceand a storage medium includes a host interface that receives from thehost device a command to transfer data between the host device and thestorage medium, a buffer that temporarily stores data that istransferred between the host device and the storage medium, and aregister that stores a value for determining the buffer's fullness.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention, as defined in the claims, can be betterunderstood with reference to the following drawings. The drawings arenot necessarily to scale, emphasis instead being placed on clearlyillustrating the principles of the present invention.

FIG. 1 is a block diagram of a computer network 100 in accordance withone embodiment of the present invention.

FIG. 2 is a block diagram depicting an embodiment of the data transfersystem depicted in FIG. 1.

FIG. 3 is a flow chart depicting a method that may be implemented by thedata transfer system depicted in FIG. 2.

FIG. 4 is a block diagram depicting an embodiment of the host interfaceof the data transfer system depicted in FIG. 2.

FIG. 5 is a block diagram depicting an embodiment of the data mover ofthe data transfer system depicted in FIG. 2.

FIG. 6 is a block diagram depicting an embodiment of the storage mediuminterface of the data transfer system depicted in FIG. 2.

FIGS. 7A, 7B, and 7C are flow charts depicting a non-limiting example ofa method for writing data to the storage medium depicted in FIG. 1 inaccordance with an embodiment of the present invention.

FIGS. 8A, 8B, and 8C are flow charts depicting a non-limiting example ofa method for reading data from the storage medium depicted in FIG. 1 inaccordance with an embodiment of the present invention.

DETAILED DESCRIPTION

FIG. 1 is a block diagram of a computer network 100 in accordance withone embodiment of the present invention. The computer network 100comprises a host 102 and a storage medium (SM) 104 that are coupled to adata transfer system (DTS) 200. In an alternative embodiment, theStorage Medium 104 and/or the Data Transfer System 200 may be part ofthe host 102. The Data Transfer System 200 facilitates read and writedata transfers between the host 102 and the Storage Medium 104. Forexample, in a write operation, data is transferred from the host 102 tothe Storage Medium 104 via the Data Transfer System 200. Similarly, in aread operation, data is transferred from the Storage Medium 104 to thehost 102 via the Data Transfer System 200. The host 102 is a dataprocessing system such as, for example, a desktop computer, a notebookcomputer, a personal digital assistant (PDA), or a mainframe computer,among others. The Storage Medium 104 is preferably a non-volatilesemiconductor memory device such as, for example, flash memory,non-volatile random access memory (non-volatile RAM), or electricallyerasable programmable read only memory (EEPROM), among others.

FIG. 2 is a block diagram depicting one embodiment of the Data TransferSystem 200 (FIG. 1). The Data Transfer System 200 includes a data mover(DM) module 500, a host interface (HI) module 400, a storage mediuminterface (SMI) module 600, a buffer 205 (preferably a circular buffer),a microprocessor 201, memory 202, and a bus 204. As indicated in FIG. 2,the components of the Data Transfer System 200 may be coupled asfollows: the Data Mover 500 is coupled to the Host Interface 400 and tothe Storage Medium Interface 600; the Host Interface 400 is coupled to ahost 102 (FIG. 1); the Storage Medium Interface 600 is coupled to aStorage Medium 104 (FIG. 1); the microprocessor 201 is coupled to thememory 202; and the Host Interface 400, the Data Mover 500, and theStorage Medium Interface 600 are coupled to the microprocessor 201 viathe bus 204. The Data Mover 500 organizes and controls the flow of databetween the host 102 and the Storage Medium 104. The buffer 205 is usedto buffer data being transferred between the host 102 and the StorageMedium 104. The memory 202 is used for storing a data transfer program203 that is executed by a microprocessor 201 to control the operation ofthe Host Interface 400, the Data Mover 500, and the Storage MediumInterface 600. In a preferred embodiment, the memory 202 comprisesrandom access memory (RAM) and read only memory (ROM), and the datatransfer program 203 comprises firmware. The buffer 205, the HostInterface 400, the Data Mover 500, the Storage Medium Interface 600, themicroprocessor 201, the memory 202, and the bus 204 are preferably, butnot necessarily, part of a single application specific integratedcircuit (ASIC).

FIG. 3 depicts a flow chart that illustrates a method 300 that may beimplemented by the Data Transfer System 200 (FIG. 2) in accordance withone embodiment of the invention. In step 301, the Data Transfer System200 receives a read or write command from the host 102 (FIG. 1)requesting a read or write operation, respectively. In response toreceiving the command, the microprocessor 201 (FIG. 2) loads registersin the Host Interface 400, the Data Mover 500, and the Storage MediumInterface 600 (FIG. 2) for executing the read or write operationrequested by the command. In a read operation, data is transferred fromthe Storage Medium 104 (FIG. 1) to the host 102. During a writeoperation, data is transferred from the host 102 to the Storage Medium104. After the registers are loaded in step 302, a data unit (e.g., ablock or a sector of data) is transferred between the Data TransferSystem 200 and the host 102 or the Storage Medium 104, as indicated instep 303. The data transfer is coordinated and managed by the HostInterface 400, the Data Mover 500, and/or the Storage Medium Interface600. Data that is transferred between the host 102 and the StorageMedium 104 is buffered in the buffer 205 of the Data Transfer System200. In one implementation of the method 300, a data unit that istransferred between the buffer 205 and the host 102 is a block of datathat may comprise multiple sectors, whereas a data unit that istransferred between the buffer 205 and the storage medium 104 is asector (e.g. 512 bytes). Data is preferably transferred between the DataTransfer System 200 and the host 102 in units of bytes (8 bits) or words(16 bits), and between the Data Transfer System 200 and the storagemedium 104 in units of bytes. After each unit of data is transferredbetween the Data Transfer System 200 and the host 102 or the StorageMedium 104, registers in the Host Interface 400, the Data Mover 500,and/or the Storage Medium Interface 600 are updated in step 304 toreflect the occurrence of the data transfer. After the registers areupdated, a determination is made by the data mover 500 in step 305 as towhether the entire read or write operation requested by the read orwrite command, respectively, is complete. If the entire read or writeoperation is complete, then the microprocessor 201 is interrupted instep 306, and the method 300 terminates in step 307. If, however, theread or write operation is not complete, then the method 300 repeatssteps 303-305 until the read or write operation is complete.

FIG. 4 is a block diagram illustrating selected components of the HostInterface 400 of the Data Transfer System 200 (FIG. 2) in accordancewith one embodiment of the present invention. The Host Interface 400interfaces with the host 102 (FIG. 1) and facilitates data transfersbetween the host 102 and the buffer 205 (FIG. 2). The Host Interface 400and the Data Mover 500 (FIG. 5) transmit signals to each other in orderto indicate their respective status and their readiness to perform acertain step. For instance, an H_XferBlk signal 403 from the Data Mover500 to the Host Interface 400 indicates that the buffer 205 is ready toprovide or receive data to/from the host 102. On the other hand, anH_BlkXferred signal 404 from the Host Interface 400 to the Data Mover500 indicates that a block of data has been transferred between thebuffer 205 and the host 102.

The Host Interface 400 includes a WordsPerBlk register 401 that isloaded at the beginning of a read or write operation with the number ofwords per block of data. A WordCtr register 402 is used for countingdown the number of words transferred during each block transfer. Priorto each block transfer, the WordCtr register 402 is loaded by receivinga value contained in the WordsPerBlk register 401. In an alternativeembodiment, the WordsPerBlk register 401 is loaded with the number oflongwords per block of data, and the WordCtr register 402 is used forcounting down the number of longwords transferred during each blocktransfer.

FIG. 5 is a block diagram depicting selected components of the DataMover 500 in accordance with one embodiment of the present invention.The Data Mover 500 includes registers containing information asdescribed in the following table:

TABLE 1 Registers that may be included in the Data Mover 500 REGISTERNAME CONTENT/DESCRIPTION Host_LW_Ptr 511 Data buffer 205 long wordaddress for transfers to/from host 102 Host_LW_Ctr 513 Long word counterfor transfers to/from host 102 Host_LW_PerBlk 506 The number of longwords per block of data HostXferSectCtr Counts number of sectors to betransferred (HXSC) 502 to/from host 102 SectsPerBlk (SPB) 504 Number ofsectors per block of data SOB_LW_Ptr 515 Start address of buffer 205EOB_LW_Ptr 516 End address of buffer 205 SMI_LW_Ptr 512 Data buffer 205long word address for transfers to/from Storage Medium 104 SMI_LW_Ctr514 Long word counter for transfers to/from Storage Medium 104SMI_LW_PerSect 507 The number of long words per sector. BuffSects 505Number of sectors in the buffer 205 MaxBuffSects 510 Size of the buffer205 DeviceXferSectCtr Counts number of sectors to be transferred (DXSC)503 to/from Storage Medium 104

The registers identified in Table 1 are used by the Data Mover 500 tomanage the transfer of data between the host 102 and the Storage Medium104. A data transfer between the host 102 and the Storage Medium 104 isinitiated in response to the Host Interface 400 receiving a read orwrite command from the host 102. After the Host Interface 400 receives aread or write command from the host 102, the Host Interface 400interrupts the microprocessor 201 which loads certain registers of themodules Host Interface 400, Data Mover 500, and Storage Medium Interface600 and then activates them (the modules 400, 500, and 600). After beingactivated, the Data Mover 500 sends a request for a block of data to theHost Interface 400 (for a write operation) or a request for a sector ofdata to the Storage Medium Interface 600 (for a read operation). Arequest for a block from the Host Interface 400 is achieved by sendingan H_XferBlk 403 signal to the Host Interface 400, whereas a request fora sector from the Storage Medium Interface 600 is achieved by sending anSMI_XferSect 508 signal to the Storage Medium Interface 600.

For a read operation, if there is room in the data transfer buffer 205and if the value of DXSC 503 is greater than 0, then the Data Mover 500requests that a sector of data be transmitted from the Storage Medium104 to the buffer 205. The Data Mover 500 performs this request bysending an SMI_XferSect 508 signal to the Storage Medium Interface 600.The Data Mover 500 also tracks the progress of the sector transfer bymanaging the DXSC 503, which the Data Mover 500 decrements by 1 aftereach successful sector transfer from the Storage Medium 104 to thebuffer 205. Eventually the DXSC 503 will go to 0, and the Data Mover 500will stop transmitting data transfer requests to the Storage MediumInterface 600. Similarly, for a write operation, as long as there isroom in the data transfer buffer 205 and the value of HXSC is greaterthan the value of SPB 504, the Data Mover 500 hardware will continue torequest that a block of data be transmitted from the host 102 to thebuffer 205 by sending an H_XferBlk signal to the Host Interface 400. TheData Mover 500 will also track the progress of the transfer by managingthe HXSC 502, which is decremented by the value of SPB after eachsuccessful block transfer from the host 102 to the buffer 205.Eventually the HXSC 502 will go to 0, and the Data Mover 500 will stoptransmitting data transfer requests to the Host Interface 400.

Data transfers between the data transfer buffer 205 and the HostInterface 400 or Storage Medium Interface 600 are preferably in units oflongwords (e.g., 4 bytes). As each longword is transferred, Data Mover500 hardware decrements either the Host_LW_Ctr 513 or the SMI_LW_Ctr 514depending on whether the transfer is to/from the host 102 or the StorageMedium 104. In addition, word counters internal to the Host Interface400 and Storage Medium Interface 600 are decremented. At the end of asector transfer to/from the Storage Medium 104, the Storage MediumInterface 600's internal word counter goes to 0, prompting it to sendthe sector acknowledgment SMI_SectXferred 509 to the Data Mover 500,which is expecting this signal because its own SMI_LW_Ctr 514 has goneto 0. If there are more sectors to be transferred (i.e., if the value ofDXSC 503 is greater than 0), then upon receipt of the SMI_SectXferred509 signal, the Data Mover 500 hardware reloads the SMI_LW_Ctr 514 fromthe register SMI_LW_PerSect 507 and issues another SMI_XferSect 508signal to the Storage Medium Interface 600. Similarly, at the end of ablock transfer to/from the host 102, the internal word counter WordCtr402 of the Host Interface 400 goes to 0 , prompting the Host Interface400 to send the block acknowledgment Host_BlkXferred 404 to the DataMover 500 which is expecting this signal because its Host_LW_Ctr 513 hasalso gone to 0. If there are more blocks to be transferred, then uponreceipt of the Host_BlkXferred 404 signal, the Data Mover 500 hardwarereloads the Host_LW_Ctr 513 from the register Host_LW_PerBlk 506 andissues another Host_XferBlk 403 signal to the Host Interface 400.

FIG. 6 is a block diagram illustrating selected components of theStorage Medium Interface 600 of the Data Transfer System 200 (FIG. 2) inaccordance with one embodiment of the present invention. The StorageMedium Interface 600 interfaces with Storage Medium 104 (FIG. 1) andtransfers data between the buffer 205 (FIG. 2) and the Storage Medium104 in response to receiving an SMI_XferSect signal 508 from the DataMover 500. After the Storage Medium Interface 600 transfers a sector ofdata between the buffer 205 and the Storage Medium 104, it transmits anSMI_SectXferred signal 509 to the Data Mover 500 confirming the datatransfer. Registers contained in the Storage Medium Interface 600include an SMI_XferLen register 601 that indicates the number of datasectors to be transferred and an SMI_XferCtr register 602 that countsdown the number of sectors transferred. The SMI_XferCtr register 602 isloaded with the value contained in the SMI_XferLen register 601 prior toeach read or write operation.

With additional reference to FIG. 5 throughout the remaining figuredescriptions, FIGS. 7A, 7B, and 7C are flow charts depicting anon-limiting example of a write method that is performed by the DataTransfer System 200 (FIG. 2) in accordance with one embodiment of thepresent invention. In step 701, the Host Interface 400 (FIG. 2) receivesa write command from a host 102 (FIG. 1). In response to receiving thewrite command, the Host Interface 400 interrupts the Microprocessor 201(FIG. 2) which, in step 702, loads the number of sectors per block intoSectsPerBlk (SPB 504), the transfer length in sectors intoHostXferSectCtr (HXSC 502) and DeviceXferSectCtr (DXSC 503), the numberof longwords in a sector into SMI_LW_PerSect 507, and the number oflongwords in a block into Host_LW_PerBlk 506. In addition, theMicroprocessor 201 sets BuffSects 505 to MaxBuffSects 510, setsHost_LW_Ptr 511 and SMI_LW_Ptr 512 to SOB_LW Ptr 505, and then activatesthe modules Host Interface 400, Data Mover 500, and Storage MediumInterface 600 (FIG. 2).

Subsequently, in step 703, the Data Mover 500 determines if the amountof data remaining to be transferred is less than a block's worth ofdata; this determination is based on whether the value of HXSC 502 isless than the value of SPB 504. If the value of HXSC 502 is less thanthe value of SPB 504, then the method 700 proceeds to step 715 (FIG.7C). If, however, the value of HXSC 502 is not less than the value ofSPB 504, then the Data Mover 500 determines in step 704 if there is atleast 1 block's worth of available storage in the buffer 205; thisdetermination is based on whether the value of BuffSects 505 is greaterthan or equal to the value of SPB 504. If the value of BuffSects 505 isnot greater than or equal to the value of SPB 504, then the method 700proceeds to step 708 (FIG. 7B).

If the value of BuffSects 505 is greater than or equal to the value ofSPB 504, then the Data Mover 500 sends an H_XferBlk 403 signal to theHost Interface 400 requesting that the Host Interface 400 transfer ablock of data from the host 102 to the buffer 205, as indicated in step705. After the H_XferBlk 403 signal is sent to the Host Interface 400, ablock of data is transferred from the host 102 to the buffer 205 in step706 and the Data Mover 500 receives an H_BlkXferred 404 signal from theHost Interface 400 confirming the data transfer. After the H_BlkXferred404 signal is received by the Data Mover 500 from the Host Interface400, the values of HXSC 502 and BuffSects 505 are decreased by the valueof SPB 504, as indicated in step 707. In addition, if the value ofHost_LW_Ptr 511 is equal to EOB_LW_Ptr 516, then the value ofHost_LW_Ptr 511 is set equal to SOB_LW_Ptr 515.

The Data Mover 500 then determines in step 708 (FIG. 7B) if data sectorsremain to be transferred to the Storage Medium 104 (FIG. 1); thisdetermination is based on whether the value of DXSC 503 is greater than0. If the value of DXSC 503 is not greater than 0, then the StorageMedium Interface 600 interrupts the microprocessor 201 in step 709 andthe method 700 terminates in step 710. If, however, the value of DXSC503 is greater than 0, then the Data Mover 500 determines in step 711 ifthere is at least one sector of data in the buffer 205; thisdetermination is based on whether the value of BuffSects 505 is lessthan the value of MaxBuffSects 510.

If the value of BuffSects 505 is less than the value of MaxBuffSects510, then the Data Mover 500 sends an SMI_XferSect 508 signal to theStorage Medium Interface 600 requesting that the Storage MediumInterface 600 transfer a sector of data from the buffer 205 to theStorage Medium 104, as indicated in step 712. However, if the value ofBuffSects 505 is not less than the value of MaxBuffSects 510, then themethod 700 returns to step 703 (FIG. 7A). After the Storage MediumInterface 600 receives an SMI_XferSect 508 signal, the Storage MediumInterface 600 transfers a sector of data from the buffer 205 to theStorage Medium 104, as indicated in step 713, and then sends anSMI_SectXferred 509 signal to the Data Mover 500 confirming thetransfer. After the SMI_SectXferred 509 signal is received by the DataMover 500, the value of DXSC 503 is decreased by 1 and the value ofBuffSects 505 is increased by 1, as indicated in step 714. In addition,if the value of SMI_LW_Ptr 512 is equal to EOB_LW_Ptr 516, then thevalue of SMI_LW_Ptr 512 is set equal to SOB_LW_Ptr 515.

At step 715 (FIG. 7C), the Data Mover 500 determines if there is a runtblock remaining to be transferred. A runt block is an amount of datathat is less than the unit of data (e.g. block) that the host 102 usesin sending or receiving data to the Data Transfer System 200. Thedetermination of whether a runt block remains to be transferred is basedon whether the value of HXSC 502 is greater than 0. If the value of HXSC502 is not greater than 0, then the method 700 proceeds to step 708(FIG. 7B). If, however, the value of HXSC 502 is greater than 0, thenthe Data Mover 500 interrupts the microprocessor 201 in step 716. Afterbeing interrupted, the microprocessor 201 reloads SPB 504 with HXSC 502and Host_LW_PerBlk 506 with a value equal to the value of HXSC 502multiplied by the value of SMI_LW_PerSect 507 (i.e. Host_LW_PerBlk 506is loaded with a value equal to the number of longwords remaining to betransferred). After SPB 504 and Host_LW_PerBlk 506 are reloaded, themethod 700 returns to step 703 so that the runt block may betransferred. After the runt block is transferred, the microprocessor 201reloads SPB 504 and Host_LW_PerBlk 506 with the values that they hadprior to when the microprocessor 201 was interrupted in step 716. In onepossible implementation, the microprocessor is not interrupted in step716; instead, SPB 504 and Host_LW_PerBlk 506 are reloaded prior to therunt block transfer using a specialized circuit without microprocessor201 intervention.

FIGS. 8A, 8B, and 8C are flow charts depicting a non-limiting example ofa read method that is performed by the Data Transfer System 200 (FIG. 2)in accordance with one embodiment of the present invention. In step 801,the Host Interface 400 (FIG. 2) receives a read command from a host 102(FIG. 1). In response to receiving the read command, the Host Interface400 interrupts the microprocessor 201 (FIG. 2) which, in step 802, loadsthe number of sectors per block into SPB 504, the transfer length insectors into HXSC 502 and DXSC 503, the number of longwords in a sectorinto SMI_LW_PerSect 507, and the number of longwords in a block intoHost_LW_PerBlk 506. In addition, the Microprocessor 201 sets BuffSects505 to 0, sets Host_LW_Ptr 511 and SMI_LW_Ptr 512 to SOB_LW_Ptr 505, andthen activates the modules Host Interface 400, Data Mover 500, andStorage Medium Interface 600 (FIG. 2).

The Data Mover 500 then determines in step 803 if data sectors are to bereceived from the Storage Medium 104 (FIG. 1); this determination isbased on whether the value of DXSC 503 is greater than 0. If the valueof DXSC 503 is not greater than 0, then the method 800 proceeds to step808 (FIG. 8B). If the value of DXSC 503 is greater than 0, then the DataMover 500 determines in step 804 if there is space in the buffer 205 forreceiving a sector of data from the Storage Medium 104; thisdetermination is based on whether the value of BuffSects 505 is lessthan the value of MaxBuffSects 510.

If the value of BuffSects 505 is not less than the value of MaxBuffSects510, then the method 800 proceeds to step 808. However, if the value ofBuffSects 505 is less than the value of MaxBuffSects 510, then the DataMover 500 sends an SMI_XferSect 508 signal to the Storage MediumInterface 600 requesting that the Storage Medium Interface 600 transfera sector of data from the Storage Medium 104 to the buffer 205, asindicated in step 805. After the Storage Medium Interface 600 receivesthe SMI_XferSect 508 signal, the Storage Medium Interface 600 transfersa sector of data from the Storage Medium 104 to the buffer 205, asindicated in step 806, and then sends an SMI_SectXferred 509 signal tothe Data Mover 500 confirming the transfer. After the SMI_SectXferred509 signal is received by the Data Mover 500 from the Storage MediumInterface 600, the value of DXSC 503 is decreased by 1 and the value ofBuffSects 505 is increased by 1, as indicated in step 807. In addition,if the value of SMI_LW_Ptr 512 is equal to EOB_LW_Ptr 516, then thevalue of SMI_LW_Ptr 512 is set equal to SOB_LW_Ptr 516.

Subsequently, in step 808 (FIG. 8B), the Data Mover 500 determines ifthe amount of data remaining to be transferred is less than a block'sworth of data. This determination is based on whether the value of HXSC502 is less than the value of SPB 504. If the value of HXSC 502 is lessthan the value of SPB 504, then the method 800 proceeds to step 815(FIG. 8C). If, however, the value of HXSC 502 is not less than the valueof SPB 504, then the Data Mover 500 determines in step 809 if there isat least 1 block's worth of data in the buffer 205; this determinationis based on whether the value of BuffSects 505 is greater than or equalto the value of SPB 504. If the value of BuffSects 505 is not greaterthan or equal to the value of SPB 504, then the method 800 proceeds tostep 803 (FIG. 8A). However, if the value of BuffSects 505 is greaterthan or equal to the value of SPB 504, then the Data Mover 500 sends anH_XferBlk 403 signal to the Host Interface 400 requesting that the HostInterface 400 transfer a block of data from the buffer 205 to the host102, as indicated in step 810. After the H_XferBlk 403 signal is sent tothe Host Interface 400, a block of data is transferred from the buffer205 to the host 102 in step 811 and the Data Mover 500 receives anH_BlkXferred 404 signal from the Host Interface 400 confirming the datatransfer. After the H_BlkXferred 404 signal is received by the DataMover 500 from the Host Interface 400, the values of HXSC 502 andBuffSects 505 are decreased by the value of SPB 504, as indicated instep 812. In addition, if the value of Host_LW_Ptr 511 is equal toEOB_LW_Ptr 516, then the value of Host_LW_Ptr 511 is set to SOB_LW_Ptr505. After the register values are adjusted in step 812, the method 800returns to step 803 (FIG. 8A).

At step 815 (FIG. 8C), the Data Mover 500 determines if there is a runtblock remaining to be transferred. The determination of whether a runtblock remains to be transferred is based on whether the value of HXSC502 is greater than 0. If the Data Mover 500 determines in step 815 thatthe value of HXSC 502 is not greater than 0, then the Data Mover 500interrupts the microprocessor 201 in step 818 and the method 800terminates in step 819. If, however, the value of HXSC 502 is greaterthan 0, then the Data Mover 500 interrupts the microprocessor 201 instep 816. After being interrupted, the microprocessor 201 reloads SPB504 with HXSC 502 and reloads Host_LW_PerBlk 506 with a value equal tothe value of HXSC 502 multiplied by the value of SMI_LW_PerSect 507(i.e., Host_LW_PerBlk 506 is loaded with a value equal to the number oflongwords remaining to be transferred). After SPB 504 and Host_LW_PerBlk506 are reloaded, the method 800 returns to step 808 so that the runtblock may be transferred. After the runt block is transferred, themicroprocessor 201 reloads SPB 504 and Host_LW_PerBlk 506 with thevalues that they had prior to when the microprocessor 201 wasinterrupted in step 816. In one possible implementation, themicroprocessor is not interrupted in step 816. Instead, SPB 504 andHost_LW_PerBlk 506 are reloaded prior to the runt block transfer using aspecialized circuit without microprocessor 201 intervention.

In an alternative embodiment of the Data Transfer System 200, functionsor steps shown in the flow charts depicted in FIGS. 7A, 7B, 7C, 8A, 8B,and 8C may be executed out of order from that shown or discussed,including substantially concurrently or in reverse order as would beunderstood by those reasonably skilled in the art.

It should be emphasized that the above-described embodiments of thepresent invention are merely possible examples, among others, of theimplementations, setting forth a clear understanding of the principlesof the invention. Many variations and modifications may be made to theabove-described embodiments of the invention without departingsubstantially from the principles of the invention. All suchmodifications and variations are intended to be included herein withinthe scope of the disclosure and present invention and protected by thefollowing claims.

1. A method for transferring data between a host device and a storagemedium via a buffer, comprising: receiving from the host device acommand to transfer data between the host device and the storage medium;storing in a first register a value for tracking a number of sectors inthe buffer available for storing data units; storing in a secondregister a vault, corresponding to a number of data units to transferduring an iteration of the transfer of the data between the host deviceand the storage medium; transferring the number of the data units intothe buffer from one of the host device and the storage medium responsiveto the command; modifying the value contained in the first register withthe value stored in the second register in response to a completediteration of the transfer of the data into the buffer; transferring thenumber of the data units out of the buffer and to another of the hostdevice and the storage medium; and modifying the value contained in thefirst register in response to a transfer of the data units out of thebuffer, wherein, during the transfer of the data between the host deviceand the storage medium, the value contained in the first registercorresponds to a number of data units currently stored in the buffer,and wherein modifying the value contained in the first register with thevalue stored in the second register is accomplished by decrementing thevalue contained in the first register by the value stored in the secondregister.
 2. The method of claim 1 further comprising: storing in athird register an address representing a location in the buffer wheredata is being transferred between the buffer and the host device; andstoring in a fourth register an address representing a location in thebuffer where data is being transferred between the buffer and thestorage medium.
 3. The method of claim 2, further comprising: storing ina fifth register an address representing a beginning of the buffer; andstoring in a sixth register an address representing an end of thebuffer.
 4. The method of claim 3, further comprising: storing in aseventh register a value representing a storage capacity of the buffer.5. The method of claim 1, wherein the host device is a computer.
 6. Themethod of claim 1, wherein the storage medium comprises non-volatilesemiconductor memory.
 7. The method of claim 1, further comprising:implementing the method via an application specific integrated circuit(ASIC).
 8. The method of claim 1, wherein modifying the value containedin the first register in response to a transfer of a data unit out ofthe buffer comprises incrementing the value contained in the firstregister.
 9. The method of claim 8, wherein incrementing comprisesincrementing the value contained in the first register by 1 responsiveto each data unit being transferred out of the buffer.
 10. A datatransfer system for transferring data between a host device and astorage medium, comprising: a host interface operative to receive fromthe host device a command to transfer data between the host device andthe storage medium; a buffer operative to temporarily store data that istransferred between the host device and the storage medium; a firstregister operative to store a value for tracking a number of sectors inthe buffer available for storing data units; and a second registeroperative to store a value for modifying the value contained in thefirst register, the value stored in the second register corresponding toa number of data units to transfer during an iteration of the transferof the data between the host device and the storage medium, wherein, intransferring the data between the host device and the storage medium,the value contained in the first register corresponds to a number ofdata units currently stored in the buffer, and wherein modifying thevalue contained in the first register with the value stored in thesecond register is accomplished by decrementing the value contained inthe first register by the value stored in the second register.
 11. Thedata transfer system of claim 10, wherein the data transfer system isconfigured to modify the value contained in the first register inresponse to a transfer of a data unit between the buffer and the hostdevice.
 12. The data transfer system of claim 11, wherein the datatransfer system is configured to modify the value contained in the firstregister in response to a transfer of a data unit between the buffer andthe storage medium.
 13. The data transfer system of claim 12, whereinthe data transfer system is configured to decrement the value containedin the first register by 1 responsive to each data unit beingtransferred out of the buffer.
 14. The data transfer system of claim 10,further comprising: a third register that stores an address representinga location in the buffer where data is being transferred between thebuffer and the host device; and a fourth register that stores an addressrepresenting a location in the buffer where data is being transferredbetween the buffer and the storage medium.
 15. The data transfer systemof claim 14, further comprising: a fifth register that stores an addressrepresenting a beginning of the buffer; and a sixth register that storesan address representing an end of the buffer.
 16. The data transfersystem of claim 15, further comprising: a seventh register that stores avalue representing a storage capacity of the buffer.
 17. The datatransfer system of claim 10, wherein the data transfer system is anapplication specific integrated circuit (ASIC).